ItInsightsWorld Silicon Watch: Synaptics Astra SR200 series Pushes Multimodal AI Fully On-Device with Custom DRAM Scaling
Placing perception workloads at the edge instead of in a datacenter has always come down to a budget question: how many model weights and how much sensor history a controller-class chip can hold. The Synaptics Astra SR200 series tackles that budget head-on, coupling heterogeneous, AI-native compute and acceleration with integrated high-bandwidth custom DRAM scalable to hundreds of Mbytes, so larger AI models and richer multimodal workloads can remain entirely on-device.
Compute stack: one engine, several accelerators
At the center of the platform sits the Torq AI engine, which builds on Google Research's transformer-capable Coral NPU to reach up to 400 GOPS of AI inference in the family's top configuration. The surrounding silicon is arranged as a general-purpose edge system rather than a bare accelerator:
- Arm Cortex-M85 and Cortex-M52 cores for control and signal processing;
- integrated vision and audio capabilities;
- hardware-rooted security.
Memory hierarchy organized in two tiers
Tightly coupled storage is capped at up to 8 Mbytes of SRAM, while the extensible, high-bandwidth, high-capacity custom DRAM absorbs what larger multimodal graphs demand. According to Synaptics, this arrangement runs workloads at one-third the power of typical system DRAM — which is precisely why memory capacity, rather than the accelerator, stops being the limiting factor for designers.
Three pin-compatible lines on one SDK
The Astra SR200 series comprises three pin-compatible product lines sharing a common hardware foundation and SDK. The lines differ mainly in accelerator headroom and in the sensing and display paths they expose:
| Product line | Target workload | AI inference | I/O characteristics |
|---|---|---|---|
| SR210 | Always-on voice and sensing | 200 GOPS | Voice-first, sensor-focused |
| SR230 | Vision plus display, with optional audio | 300 GOPS | Adds vision and display paths |
| SR250 | Demanding edge applications | 400 GOPS | Dual vision and display paths |
How the tier ladder is meant to be used
For teams standardizing on a single board design, the practical benefit is choosing a compute tier without re-engineering the platform: 200 GOPS for listening-only products, 300 GOPS once vision and a display enter the picture, and 400 GOPS where two simultaneous vision and display paths are required. The scaling custom DRAM — extendable to hundreds of Mbytes at one-third the power of typical system DRAM — is what makes that ladder usable on real devices instead of on a reference board.