CoWoS Bottleneck Deepens: Packaging Lead Times, Test Cycles and the Rumored 2027 TSMC Price Reset
Read the AI silicon supply chain from the back end forward and the picture changes: the binding constraint is increasingly the packaging and test work that sits behind lithography. CoWoS is TSMC's advanced packaging family for high-performance chips, and its trick is a silicon interposer that ties compute dies together with high-bandwidth memory (HBM) inside one package. Growth in AI accelerator demand has pulled more orders into that flow, and the interest now reaches past AI GPUs into server CPUs and custom ASICs, leaving the undelivered backlog along the chain still building.
The numbers behind the squeeze
| Reported signal | Figure | Source of the figure |
|---|---|---|
| Equipment delivery window, previously | 3 to 6 months | Supply chain reports |
| Equipment delivery window, now | 6 to 8 months | Supply chain reports |
| Nvidia Blackwell final-test time versus Hopper | About 4x | Nomura estimate |
| Nvidia Rubin final-test time versus Hopper | Potentially 7x | Nomura estimate |
| Wafer foundry price increase planned from January 2027 | About 3% to 6%, with the largest steps on 2 nm and 3 nm | Taiwan media citing supply chain information |
| GlobalFoundries silicon interposer agreement serving the TSMC CoWoS chain | $2 billion, multi-year | Company announcement |
Buyers have stopped negotiating on equipment
Pressure is visible on both sides of the line, packaging and test. The equipment needed for those steps now arrives on a 6 to 8 month schedule, against the 3 to 6 months quoted before. Customer behaviour has shifted with it: procurement teams are paying for guaranteed delivery and have dropped the price cuts and extra functions they used to press TSMC for when ordering tooling.
Test time is the quieter variable. Nomura's estimate puts final testing of Nvidia's Blackwell at roughly 4x the duration of Hopper, with Rubin potentially reaching 7x. Those are analyst numbers rather than company guidance, and their significance is capacity: every additional hour a die spends on the tester is an hour that burn-down capacity cannot be redeployed to the next generation of packages.
Pricing: a rumour the foundry has not confirmed
Beyond CoWoS packaging quotes, media in Taiwan reported earlier that TSMC intends to lift wafer foundry prices by about 3% to 6% starting January 2027, with advanced nodes such as 2 nm and 3 nm taking the steepest share of the increase. This, too, rests on supply chain information, and TSMC has not publicly confirmed a specific magnitude.
What has actually been announced
At its recent investor briefing, TSMC said AI-related demand is robust and that it is moving faster on capacity expansion. A CoWoS package at 5x reticle area is already in mass production, even larger formats are under development, and the company is advancing CoPoS technology. On the partner side, GlobalFoundries has signed a multi-year, $2 billion manufacturing agreement with TSMC to produce silicon interposers at its New York State facility for the CoWoS supply chain, with volume ramp targeted in the first half of 2028 — timing that does little to ease the constraint felt today.
Who absorbs the increase, and who is largely insulated
If the higher prices are implemented, the bill lands first on the products that actually use CoWoS: AI accelerators and data centre silicon. Gaming graphics cards typically do not go through this packaging route, so a CoWoS quote increase does not reach them directly. A broader wafer foundry price adjustment is a different matter, since it can travel gradually into other chips and, from there, into end devices.